Figure 1 - Electrochemical etched trench in silicon
Figure 1 - Electrochemical etched trench in silicon
On p-type Si wafers (10 - 20 Ohmcm, (100) orientation) nitride layers with varying thickness were deposited with a standard PECVD process and structured with standard lithographic processes. KOH pits were chemically etched. It has been shown that KOH pits can be used as starting points for macropores on p- and n-type silicon. The free silicon surfaces were defined with the nitride windows for etching random p-type macropores and arrays of pits for prestructured macropores. Pore etching was performed in an electrochemical cell. A computer controlled all parameters of the measurement setup. The temperature of the electrolyte was constant at 20°C. The electrolyte consisted of 4 wt.-% HF in organic dimethylformamide (DMF). Galvanostatic experiments with current densities between were performed.
The trench formation is connected with a minimal under-etch of the nitride-mask. The trench grows
parallel to nitride-layer on the silicon over several hundred micrometers. The trench width is decreasing
with the distance from the surface: 5 - 1 µm. The growth rate of the trench is 10 µm/min, this means about
10-times higher than the macropore growth rate. The trench grows perpendicular to the surface in <100>-direction.
In the nucleation phase of the trench also macropores are formed.
Figure 2 - SEM micrograph of the trench in silicon)
One example for the use of this technique are full isolated CMOS structures.
Pore Etching in 150 mm p-type Wafers
Most applications envisioned call for the etch-ing of standard size Si wafers,
at least 100 mm, better yet 150 mm or 200 mm. While any etch-ing recipe that produces
satisfying pores with small samples of typically (1 – 4) cm2 will of course also work for
larger wafers if the proper conditions can be maintained everywhere on the surface, there
are a number of specific technical problems to large area etching which are not easy to solve.
Macropores on p-type Si – either in aqu. or org. electrolytes – do not require illumination
which makes cell design easier (but with the added complexity of sever restrictions in usable materials).
A design suitable for 150 mm wafers is now operative.
The cell has been constructed from PVC for the trial and error period which presently
limits the use of organic electrolytes. So far, mostly p-macropores(aqu) were etched (p-macropores (org)
have to await a reconstruction with TeflonTM for the crucial parts). Fig. 3 shows a etched p-type wafer. Additional SEM micrographs
from other
parts of the wafer demonstrated that homogeneous pore etching was achieved everywhere on the wafer.
Etching micro- and mesopores of just a few micrometers in depth on large areas is a com-paratively easier task.
The ELTRANTM process by CanomTM obviously has mastered this; but little is known
about the cell design except that an electrolyte backside contact is used and several wafers are processed
at the same time. The ELTRANTM process is an industrial level SOI wafer production with the use of a
mesoporous silicon sacrificial layer.
Figure 3 - First full etched 6" p-type Wafer
Applications of macropores Macropores offer a number of attractive fea-tures for many kinds of applications. A listing includes:
There are, however, also some difficulties in employing macropores for products. These may be listed as follows:
While there are many known modes of pore etching in Si (and possibly more to be discovered), a general
understanding of the formation processes has not yet been achieved. Technical uses of macropores are
nevertheless possible, and a rapidly growing number of applications is under investigation. While large area
etching is not easy, it is possible and has been demonstrated.